Performance Analysis of Parallel FIR Digital Filter using VHDL

With the continuing trends to reduce the chip size and integrates multichip solution into a single chip solution it is important to limit the silicon area required to implement parallel FIR digital filter in VLSI implementation. The Need for high performance and low power digital signal processing is getting increased. Finite Impulse Response (FIR) filters are one of the most widely used fundamental devices performed in DSP system. This paper presents the performance analysis of parallel FIR digital filter, In this paper, Traditional FIR filter structure and FFA based FIR filter structure and symmetric convolution based FFA FIR filter are designed for 2-parallel filter (2*2). These entire filter structures are designed based on Carry Save Adder (CSA) and Ripple Carry Adder (RCA).Exchanging multipliers with adder is advantageous because adders weight less then multipliers in terms of silicon area. The performance of parallel FIR filter structure based on Ripple Carry Adder and Carry Save Adder will be compared.